The SCAmpR architecture is a new approach to high-end data acquisition. As the name suggests, each amplifier in the system has memory for storing data. In addition, each amplifier has a microprocessor that configures the amplifier for different requirements and calibrates, communicates, and processes the data. In short, each amplifier is a stand-alone data acquisition system.

A SCAmpR channel communicates using a standard network protocol conforming to American National Standards Institute/Institute of Electrical and Electronics Engineers (ANSI/IEEE) STD 802.1. This enables the system to be integrated using standard network distribution equipment. The system is commanded and data is retrieved from the SCAmpR channels through an isolated network using a simple software application written for a personal computer (PC) running Windows. This application can be adapted to other computer platforms.

The intent of this architecture is to time-tag and record the data at the amplifier in nonvolatile memory. This greatly increases the reliability of the system by eliminating the possibility of failures in peripheral components that are required for recording data in traditional systems. With SCAmpR, the data is archived at the source and can be retrieved at any time. Even if there is a failure while retrieving the data, the retrieval process can, at worst, just be repeated. The system is designed with bandwidth that allows for data snapshots to be acquired by the host PC while receiving health status from the SCAmpR channels. In fact, the data files in their entirety can be transferred while recording for a 200-channel system operating at 10,000 samples per second per channel.

The system is designed around ANSI/IEEE 1014, specifically referencing the 6U VersaModule Eurocard (VME), 21-slot mechanical standard. This makes standard VME hardware suitable for the chassis buildup. This standardization greatly reduces cost and ensures continued availability of chassis parts through numerous vendors. A single chassis will contain 64 SCAmpR channels and mount in a standard 19-inch rack. The backpanel of the chassis will have the sensor cable interface connectors. These can be built to integrate with existing systems. The prototype chassis is shown in the figure.

The system is scalable to the limits of the network equipment. The individual SCAmpR channels communicate at 100 megabits per second. The chassis is configured to interface with a single network cable. This greatly reduces infrastructure costs.

The system in no way adheres to the electrical VME standard. The chassis uses the backplane for power distribution to the SCAmpR channels. The two end slots on both sides of the chassis contain modularly designed power cards that provide power for 16 SCAmpR channels through the backplane. The chassis can be configured to require a single 120-volt alternating current power cable or accept a 28-V direct current power source. Any power slot can receive any power module.

The 6U form factor allows space for four SCAmpR channels to be located in a single card slot. The channels share no hardware though they reside on the same circuit board. This ensures that a failure of any one channel will be isolated and affect no other channel.

SCAmpR Prototype Chassis Showing 16-Channel Power Module

The approach to the SCAmpR channel is also modular. Though the processor, communication, and memory will be the same, it is anticipated that different requirements will necessitate the design of specialized amplifier sections. A section of the circuit board is reserved for varying measurement requirements. It will be relatively inexpensive to integrate a specialized requirement into the basic modular design.

The final card slot of the chassis is reserved for a certification card. This system will not require a separate certification station. A single command from the host PC will initiate a certification cycle that will confirm the health of the chassis and its contents. This feature will save considerable labor. The system will not have to break configuration to achieve the required annual calibration of the amplifiers. A periodic calibration of the certification card is all that will be required.

The SCAmpR architecture was created with the intent of breaking the pattern of increasingly short-duration obsolescence associated with electronic systems. This system can adapt readily to changes in network equipment. With a simple software application revision, computer equipment and operating systems can be replaced without major cost or time impact to the system. SCAmpR will continue the tradition of state-of-the-art data acquisition at KSC while reducing costs for operation and maintenance to a fraction of that required in current systems.

Key accomplishments:

• Developed system requirements.
• Prototyped power module, SCAmpR module, backplane, and chassis.
• Tested and demonstrated the system prototype.

Contact: J.M. Perotti (Jose.Perotti-1@ksc.nasa.gov), YA-D2-E1, (321) 867-6746
Participating Organization: Dynacs Inc. (Dr. P.J. Medelius, J.D. Taylor, J.A. Rees, Dr. C.T. Mata, J.J. Henderson, and T. Erdogan)